Search - vhdl encoder

[Communication-Mobile] serialparallel

Description: BCH编码器并行8路实现，速率达到300M以上-BCH encoder realize 8-channel parallel, the rate reached more than 300M
Platform: | Size: 2048 | Author: 张凯斌 | Hits:

[VHDL-FPGA-Verilog] crc_verilog

Description: 循环码编码器verilog实现，里面包含有源程序和仿真图。-Cyclic code encoder Verilog realization, which contains the source code and simulation of Fig.
Platform: | Size: 15360 | Author: 萍果 | Hits:

[Streaming Mpeg4] H.264

Description: 本书在介绍数字视频和视频编码的基本原理基础上，论述了H264的特点、编码器原理、解码器原理以及编解码器的实现方案。-This book, introducing digital video and video encoding based on the basic principles, discusses the characteristics of H264, encoder principle, the principle of the decoder and codec realization of the program.
Platform: | Size: 11018240 | Author: 许菀纯 | Hits:

[Other Embeded program] qep

Description: 一个QEP电路的verilog代码。输入信号是光电编码器的A相和B相信号和一个处理时钟，输出的是计数信号和方向信号。-A QEP circuit Verilog code. Input signal is the optical encoder of the A phase and B and believe that a deal with the clock, the output is the count signal and direction signal.
Platform: | Size: 1024 | Author: 张洁 | Hits:

[Compress-Decompress algrithms] rs_encoder

Description: 一个很不错RS编码，用于DVB的信道编码，用VHDL语言编写，在FPGA上通过验证。-A very good RS encoder for DVB Channel Coding using VHDL language, in the FPGA-validated.
Platform: | Size: 3072 | Author: 杨宇 | Hits:

[Wavelet] compressVLSI

Description: 高速图像压缩编码器的VLSI结构设计研究.kdh 相当有水平的博士论文。里面详细讲到了如何设计小波变换VLSI结构。并对verilog hdl设计结构进行了评估-High-speed image compression encoder the structural design of VLSI Research. Kdh quite the level of doctoral dissertation. Which describes in detail how to design the structure of wavelet transform VLSI. Verilog hdl design and structure of the assessment
Platform: | Size: 1733632 | Author: 黄辉 | Hits:

[Software Engineering] AB_PHASE_PWM_SOPC

Description: AB相编码器解码接口、PWM输出SOPC议案及其在运动控制卡和伺服驱动器中的应用-AB phase encoder decoder interface, PWM output SOPC motion and in motion control card and servo drive applications
Platform: | Size: 402432 | Author: 张贺 | Hits:

[VHDL-FPGA-Verilog] 5050PWM_V54

Description: FPGA 实现基于ISA接口的3路编码器计数，和3路PWM/DA输出编码器计数包括倍频、鉴相 PWM实现12位分辨率-FPGA-based ISA interface 3 Road encoder counts, and 3-way PWM/DA output encoder counts, including frequency doubling, phase PWM realize 12-bit resolution
Platform: | Size: 1084416 | Author: 吴波 | Hits:

[Communication-Mobile] RSencoder

Description: 关于rs码编码器的相关程序，利用硬件语言实现-Rs encoder code on the relevant procedures, take advantage of the hardware language
Platform: | Size: 5120 | Author: 庄镒鹏 | Hits:

[VHDL-FPGA-Verilog] viterbi

Description: 卷积码编码及其Viterbi译码的实现-Convolutional code encoder and Viterbi decoding to achieve
Platform: | Size: 256000 | Author: mediative | Hits:

[VHDL-FPGA-Verilog] bianma

Description: 用VHDL语言实现8-3线编码器，16-4线编码器-VHDL language used to achieve 8-3 line encoder ,16-4-wire encoder
Platform: | Size: 1024 | Author: wangmixia | Hits:

[VHDL-FPGA-Verilog] s3esk_rotary_encoder_interface

Description: 旋转编码器的decoder，具有消颤音功能-Rotary encoder decoder, with a vibrato function elimination
Platform: | Size: 280576 | Author: 于水 | Hits:

[VHDL-FPGA-Verilog] encoder

Description: vhdl的七段译码器-The Seven-Segment Decoder VHDL
Platform: | Size: 3072 | Author: tgfire | Hits:

[VHDL-FPGA-Verilog] crcm

Description: crc 校验，vhdl源码，经仿真能正常运行，供大家参考-CRC checksum, vhdl source, the simulation can be normal operation, for your reference
Platform: | Size: 1024 | Author: fangliang | Hits:

[File Format] Manchester

Description: “Manchester码（双相码）编码器- Manchester Code (two-phase code) encoder
Platform: | Size: 1024 | Author: 冯小晶 | Hits:

[VHDL-FPGA-Verilog] coder

Description: 这是用VHDL语言编写的3-8编码器，可以看到程序简单可行-This is the language used VHDL encoder 3-8, we can see that the procedure is simple and feasible
Platform: | Size: 20480 | Author: chenxiaoming | Hits:

[Special Effects] video_process_base_on_DSPandFPGA

Description: 基于高速数字信号处理器(DSP) 和大规模现场可编程门阵列( FPGA) ,成功地研制了小型化、低功耗的实时视频采集、处理和显示平台. 其中的DSP 负责图像处理,其外围的全部数字逻辑功能都集成在一片FPGA 内,包括高速视频流FIFO、同步时序产生与控制、接口逻辑转换和对视频编/ 解码器进行设置的I2 C 控制核等. 通过增大FIFO 位宽、提高传输带宽,降低了占用EMIF 总线的时间利用数字延迟锁相环逻辑,提高了显示接口时序控制精度. 系统软件由驱动层、管理层和应用层组成,使得硬件管理与算法程序设计彼此分离,并能协同工作. 系统中的图像缓冲区采用了三帧的配置方案,使得该平台最终具有对PAL/ N TSC 两种制式的全分辨率彩色复合视频信号进行实时采集、显示和处理的能力.-Based on high-speed digital signal processor (DSP) and large-scale field programmable gate array (FPGA), successfully developed a smaller, low-power real-time video capture, processing and display platform. One of the DSP is responsible for image processing, all its external digital logic functions are integrated in a FPGA, including high-speed video streaming FIFO, synchronous sequential generate and control, conversion and interface logic for video encoder/decoder to set up the control of nuclear and other I2 C. through increased FIFO bit width, increase the transmission bandwidth, reducing the time occupied by EMIF bus delay phase-locked loop using digital logic,
Platform: | Size: 546816 | Author: John | Hits:

[VHDL-FPGA-Verilog] dp_test

Description: 本程序是用VHDL语言编写的，其中包括并口通讯，DDS电机调速,编码器信号处理等，对研究这方面的工程人员有一定参考作用-This procedure is used VHDL language, including the parallel port communication, DDS motor, encoder signal processing and so on, to look at this area of engineering staff have a certain reference
Platform: | Size: 602112 | Author: maolianghu | Hits:

[Crack Hack] 8b10b

Description: 8b_10b encoder/decoder
Platform: | Size: 69632 | Author: dinesh | Hits:

[VHDL-FPGA-Verilog] rs-codec-8-16

Description: RS[255,223]纠错码verilog源码，包含编码和解码模块，以及testbench等。-Verilog source code for RS[255,223] encoder and decoder, with testbench included.
Platform: | Size: 27648 | Author: 饶进平 | Hits:

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